apic_pm_state.apic_id = apic_read(APIC_ID);
apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
apic_pm_state.apic_ldr = apic_read(APIC_LDR);
- if ( !x2apic_enabled )
- apic_pm_state.apic_dfr = apic_read(APIC_DFR);
+ apic_pm_state.apic_dfr = apic_read(APIC_DFR);
apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
{
unsigned int l, h;
unsigned long flags;
- int maxlvt = get_maxlvt();
+ int maxlvt;
if (!apic_pm_state.active)
return 0;
apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
apic_write(APIC_ID, apic_pm_state.apic_id);
- if ( !x2apic_enabled )
- apic_write(APIC_DFR, apic_pm_state.apic_dfr);
+ apic_write(APIC_DFR, apic_pm_state.apic_dfr);
apic_write(APIC_LDR, apic_pm_state.apic_ldr);
apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
+ maxlvt = get_maxlvt();
if (maxlvt >= 6) {
apic_write(APIC_CMCI, apic_pm_state.apic_lvtcmci);
}
static __inline void apic_wrmsr(unsigned long reg, u32 low, u32 high)
{
+ if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
+ reg == APIC_LVR)
+ return;
+
__asm__ __volatile__("wrmsr"
: /* no outputs */
: "c" (APIC_MSR_BASE + (reg >> 4)), "a" (low), "d" (high));
static __inline void apic_rdmsr(unsigned long reg, u32 *low, u32 *high)
{
+ if (reg == APIC_DFR)
+ {
+ *low = *high = -1u;
+ return;
+ }
__asm__ __volatile__("rdmsr"
: "=a" (*low), "=d" (*high)
: "c" (APIC_MSR_BASE + (reg >> 4)));